1. Field of the Invention
The present invention relates to a semiconductor memory device and more particularly, to a semiconductor memory device each memory cell of which is comprised of a select transistor and a ferroelectric storage capacitor for electric-charge storing.
2. Description of the Prior Art
FIG. 1 shows a memory cell structure of a conventional semiconductor memory device of this sort, which is disclosed in the Japanese Non-Examined Patent Publication No. 4-144282 published in May 1992.
This conventional semiconductor memory device has a lot of memory cells 800 with a same structure, which are arranged in a matrix array. However, only two ones of the cells 800 are shown in FIG. 1 for the sake of simplification of description.
As shown in FIG. 1, each of the memory cells 800 has a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) 600 serving as a select transistor and a storage capacitor 700 for electric-charge storing.
The MOSFET 600 is formed by a source region 107s and a drain region 107d formed in a semiconductor substrate (not shown), and a common gate electrode 151 formed over the substrate through a gate oxide layer (not shown). The common gate electrode 151 serves as word lines electrically connecting the corresponding gate electrodes 151 to one another.
The drain region 107d is electrically connected to an overlying bit line 152 through a contact hole 153.
The source region 107s is electrically connected to an overlying wiring layer 104 through a contact hole 103. The wiring layer 104 is electrically connected to an underlying upper electrode 102 of the storage capacitor 700. Thus, the source region 107s is electrically connected to the overlying upper electrode 102 of the storage capacitor 700.
The storage capacitor 700 has a square-shaped ferroelectric 101 sandwiched by a strip-shaped, common lower electrode 109 and the square-shaped upper electrode 102. The common lower electrode 109 extends along a word line 151 perpendicular to the bit line 1152. The ferroelectric 101 has a slightly wider area than the upper electrode 102. The ferroelectric 101 has a same width as the lower electrode 109.
The lower electrode 109 is electrically connected to an overlying wiring layer 114 through a contact hole 112. The wiring layer 114 is electrically connected to an overlying wiring layer 154 through a contact hole 115. Thus, the lower electrode 109 is electrically connected to the wiring layer 154. The wiring layer 154 extends along the lower electrode 109 and is overlapped therewith.
As described above, in the conventional memory cell structure shown in FIG. 1, the common lower electrode 109 is commonly used by the memory cells 800 arranged along the word line 151.
FIGS. 2A to 2C show a memory cell layout of another conventional semiconductor memory device, where a lot of memory cells 800 with substantially the same structure as shown in FIG. 1 are arranged in a matrix array. FIG. 3 shows a cross section along the line III--III in FIG. 2A.
As clearly shown in FIGS. 2B and 3, source regions 107s and drain regions 107d of MOSFETs 600 are formed in a semiconductor substrate 110. Gates electrodes 151, which serve as word lines, are arranged over the substrate 110 through corresponding gate oxide layers 108a. Each pair of the source and drain regions 107s and 107d are located at each side of a corresponding one of the gate electrodes 151.
Bit lines 152 are formed on an interlayer insulating layer 108b covering the gate electrodes or word lines 151. The bit lines 152 are contacted with and electrically connected to the corresponding drain regions 197d through corresponding contact holes 153 penetrating the interlayer insulating layer 108b.
Strip-shaped lower electrodes 109 of storage capacitors 700 are formed on an interlayer insulating layer 108c covering the bit lines 152. The lower electrodes 109 extend along the word lines 151. Square-shaped ferroelectrics 101 of the storage capacitors 700 are formed on the corresponding square-shaped lower electrodes 109. Square-shape upper electrodes 102 of the storage capacitors 700 are formed on the corresponding ferroelectrics 101.
Each of the ferroelectrics 101 has a same area as a corresponding one of the lower electrodes 109. In other words, each of the ferroelectrics 101 is entirely overlapped with a corresponding one of the lower electrodes 109. Each of the upper electrodes 102 has a narrower area than a corresponding one of the lower electrodes 109. In other words, each of the upper electrodes 102 is included in a corresponding one of the ferroelectrics 101
The storage capacitors 700 are located just over the corresponding drain regions 107d or just over the positions between the adjoining source regions 107s.
Wiring layers 104 are formed on an interlayer insulating layer 108d covering the storage capacitors 700. The wiring layers 104 are contacted with and electrically connected to the upper electrodes 102 through corresponding square-shaped contact holes 105 penetrating the interlayer insulating layer 108d. The wiring layers 104 are further contacted with and electrically connected to the source regions 107s through corresponding square-shaped contact holes 103 penetrating the interlayer insulating layers 108d, 108c, and 108b.
The wiring layers 104 are covered with an interlayer insulating layer 108e.
Here, it is supposed that one side of the square-shaped upper electrode 102 has a length of a, the side length a of the upper electrode 102 and the width of the lower electrode 109 has a difference of d, the opposing ends of the lower electrode 109 and the corresponding contact hole 105 has a distance of x, one side of the square-shaped contact hole 105 has a length of c, and the opposing ends of the adjoining upper electrodes 109 has a distance of y. Then, the chip area Sc of each memory cell 800 is expressed by the following expression (1). ##EQU1##
If the difference d is increased to (d+.DELTA.d), the chip area Sc is expressed as the following expression (2). EQU Sc=(a+d+.DELTA.d+c+2x).multidot.(a+y) (2)
Therefore, the chip area Sc is increased by EQU .DELTA.d.multidot.(a+y).multidot.
For example, if the size difference d is set as a small value of 0.2 .mu.m, the remanent polarization of the ferroelectric layers 101 tends to degrade to approximately 60% of its inherent value after the formation processes of the storage capacitors 700. This is because the side ends of ferroelectrics 101 extending in parallel to the word lines 151 are damaged due to the etching or milling action during the patterning process for the ferroelectrics 101.
Therefore, to prevent this damage, the size difference d needs to be set as approximately 1.0 .mu.m or more. In this case, however, this large value of the difference d will cause a problem that the chip area Sc of the memory cell 800 is increased. This problem prevents higher integration of the memory cells 800.
In the case where the size difference d is set as 0.2 .mu.m, if a=2.0 .mu.m, x=0.6 .mu.m, c=0.9 .mu.m, and y=2.0 .mu.m, the chip area Sc is given from the above expression (1) as follows. EQU (2.0+0.2+0.9+2.times.0.6).multidot.(2.0+2.0)=17.2 .mu.m.sup.2
On the other hand, when only the size difference d is increased to 1.0 .mu.m, the chip area Sc is given as follows. EQU (2.0+1.0+0.9+2.times.0.6).multidot.(2.0+2.0)=20.4 .mu.m.sup.2
Therefore, by increasing the size difference d by 0.8 .mu.m, the chip area Sc is increased by 3.2 .mu.m.sup.2 (which is equal to approximately 19% of 17.2 .mu.m.sup.2).
Next, the reliability degradation due to parasitic capacitance is explained below.
In the conventional semiconductor memory device shown in FIGS. 2 and 3, the lower electrodes 109s are strip-shaped and extend along the word lines 151. Therefore, the parasitic capacitance between the lower electrodes 109 and any adjoining electrically-conductive lines such as the word lines 151 is small. However, if a specific one of the electrically-conductive lines located in the vicinity of the lower electrodes 109 is subjected to a large electric-potential change, and at the same time, the parasitic capacitance between the specific electrically-conductive line and the lower electrodes 109 is comparatively large, the electric potential of the lower electrodes 109 tends to fluctuate or deviate due to the electric-potential change of the specific electrically-conductive line.
For example, if each of the strip-shaped lower electrodes 109 has a parasitic capacitance of 0.6 fF, the electric potential of the lower electrodes 109 will deviate by 60 mV due to an electric-potential change of 5 V of a specific one of the electrically-conductive lines, where EQU 5 V.multidot.(0.6 fF/50 fF)=60 mV.
As described above, The conventional semiconductor device shown in FIGS. 2A to 2C and FIG. 3 has the following problems:
First, if the size difference d between the upper electrodes 102 and the ferroelectrics 101 is increased to a specific value to avoid the degradation of the characteristic of the storage capacitors 700 due to the damage applied in its formation process, the chip area Sc of the memory cells 800 is increased. This prevents higher integration of the cells 800.
Second, if a specific one of the electrically-conductive lines located in the vicinity of the lower electrodes 109 is subjected to a large electric-potential change, the electric potential of the lower electrodes 109 tends to fluctuate or deviate due to the electric-potential change of the specific electrically-conductive line.